The present invention relates to testing integrated circuits (ICs) and, more particularly, to testing an integrated circuit with a low power scan system.
Scan chains are widely used in integrated circuits (IC) to obtain access to internal nodes of an IC to simplify testing of the IC by passing test data through flip-flops of the IC. FIG. 1 is a schematic block diagram of a conventional scan system 100 including a plurality of scan chains 102 arranged in parallel to each other. Each scan chain 102 is formed by a plurality of cascaded flip-flop cells 104.
FIG. 2 is a schematic block diagram of one of the flip-flop cells 104 of FIG. 1. The flip-flop cell 104 includes a master latch 106, a slave latch 108 having an input terminal connected to an output terminal of the master latch 106, and a multiplexer 110 having an output terminal connected to an input terminal of the master latch 106. The flip-flop cell 104 is configured to operate in one of two modes, functional mode and scan mode. The multiplexer receives a data input signal (D) and a scan data input signal (SDI), and generates a first data signal depending on a scan enable signal, which is active in the scan mode. A clock signal is provided to both the master and slave latches.
For a full scan design, during scan testing, all of the flip-flop cells 104 in the IC and all of the combinational logic cells connected to the flip-flop cells 104, may be toggling at the same time, causing very high power consumption. This high power consumption is much greater than the power consumption in normal functional mode where only some of the combinational logic and flip-flops are toggling, and such high power consumption may exceed the IC's power rating. Further, as IC chip density and speed increase, the scan shift power problem is exacerbated. Therefore, there is a need for providing a low power scan system.